How It Works Validation Use Cases IP Package ceo@rpu-micro.com
Silicon-Proven · PCT/IB2026/053070 · IEEE TVLSI Under Review

The Reflex Layer
Every SoC Is Missing

A platform-agnostic synthesizable hardware IP that intercepts your data stream before the CPU. Works with any SoC, any node, any sector — without touching your existing system.

✦  Data unchanged → CPU never wakes.
✦  Data changes → CPU wakes in exactly 2 clock cycles.
✦  No software. No PMU. No polling loop. Ever.
See How It Works ↓
0%CPU Cycle Reduction
2 cycDeterministic Wake
625 MHzTSMC 65nm · 0ps Slack
2,960Gate Count
1.70 mWTotal Power
15×Toggle Reduction
101 INPUT 102 STATE 103 ΔC/Δt 104 THRESH 105 ICG / POWER-GATE Reconfig 106 OUTPUT UNIT 107 GUARDIAN Sideband (ungated) in_data in_valid clk rst_n wake_en alert_o PCT/IB2026/053070 · 2,960 gates · rpu_ultimate_final TSMC 65nm 625MHz · SKY130 100MHz
TSMC 65nm · 625 MHz · 0ps Slack SkyWater SKY130 · 0.014mW FPGA Nexys A7-100T · 15× Toggle lowRISC Ibex · 99.998% Cycle Reduction PCT/IB2026/053070 IEEE TVLSI Under Review Design & Reuse Listed 2-Cycle Deterministic Wake TSMC 65nm · 625 MHz · 0ps Slack SkyWater SKY130 · 0.014mW FPGA Nexys A7-100T · 15× Toggle lowRISC Ibex · 99.998% Cycle Reduction PCT/IB2026/053070 IEEE TVLSI Under Review Design & Reuse Listed 2-Cycle Deterministic Wake
How It Works

Two wires in.
One wire out.
Nothing else changes.

RPU operates as a fully independent block. You connect it in parallel with your existing data path — it observes your sensor bus and generates a single interrupt to your CPU when genuine change is detected.

Your SoC does not change. Your bus does not change. Your firmware does not change. If RPU is ever bypassed or removed, the system reverts to its previous polling behavior with zero added latency — guaranteed pass-through.

The entire integration is three parameter settings and two wire connections:

// 1. Set parameters for your interface rpu_ultimate_final #( .DEPTH(32), // sliding window depth .DATA_WIDTH(12) // your ADC/sensor width ) u_rpu ( .clk (sys_clk), .rst_n (sys_rst_n), // 2. Connect your data source .in_data (sensor_data[11:0]), .in_valid (data_valid), // 3. Route interrupt to CPU .wake_en (irq_external_i) );
System Integration View
Input ①
in_data[11:0]
Your sensor / ADC / bus output
Input ②
in_valid
Data valid strobe from your interface
Output
wake_en
→ CPU irq_external_i pin
Source
Sensor / ADC
12-bit stream
ADC · SPI · I2C · UART
in_data
in_valid
Hardware IP
RPU Block
rpu_ultimate_final
2,960 gates · 1 clock cycle
101Input
102State
103ΔC/Δt
104Thresh
105ICG/PG
107Guard
wake_en
irq
Processor
CPU / SoC
WFI sleep
Wakes in 2 cycles
What happens inside RPU — 1 clock cycle
1. Circular ring buffer updates (DEPTH=32) — O(1), no loop
2. Binary-divided window: delta = |avg_new − avg_old| via bit-shift
3. Adaptive threshold compare: asymmetric step_up / step_dn
4. event_next directly drives ICG enable — one combinational wire
Fail-safe guaranteed: if RPU is bypassed or removed, the system reverts to polling with zero added latency. No degradation. No risk.
Validation

Four independent evidence layers

Not simulation-only. Two ASIC nodes, one live FPGA measurement, and a complete cycle-accurate RISC-V SoC integration.

ASIC · TSMC 65nm GP

625 MHz. Clean Timing Closure.

0 ps WNS. 0 violating paths. 1.702 mW total. 2,960 gates. Cadence Genus. Critical path: 37 failing → 0 violations.

1.70 mW
ASIC · SkyWater SKY130

Same RTL. Different Node.

100 MHz. 0 ps WNS. 0.014 mW leakage — 0.35% of total. Identical RTL — no redesign required between nodes.

0.014 mW
FPGA · Nexys A7-100T

Real Sensor. Real Hardware.

LDR sensor on Vivado Power Analyzer. Live data stream fed simultaneously to conventional circuit AND RPU. Direct hardware comparison, zero variables.

15× toggle
RISC-V · lowRISC Ibex · Verilator 5M cycles

Three Scenarios — Terminal Results

Cycle-accurate simulation. Wake latency: exactly 2 cycles in all scenarios.

ScenarioPollingRPUSaving
Stable + Noise5,000,00012599.998%
Sudden Spike5,000,00033899.993%
Slow Drift5,000,0001,487,14370.3%
Applications

One IP. Seven Sectors.

The cheapest computation is the one that never occurs. RPU suppresses unnecessary computation at the source — before it propagates downstream.

Defense / Radar

Radar & Signal Intelligence

Suppress stagnant returns at hardware layer. Guardian Sideband provides ungated watchdog on critical interrupt paths.

Details →
UAV / ADAS

Autonomous Systems

LiDAR and camera stagnant frame suppression when vehicle is stationary. Zero latency penalty.

Details →
IoT / Medical

Battery-Powered Endpoints

Cardiac monitors, glucose sensors, environmental nodes. CPU stays in WFI until data actually changes.

Details →
Data Centers

SmartNIC / DPU Interfaces

Suppress unchanged telemetry before it triggers CPU interrupts and context switches.

Details →
Edge AI

AI Inference Pipelines

Suppress stagnant tensors before GPU/TPU cycles are consumed. Static scene detection at front-end.

Details →
Industrial

Predictive Maintenance

Vibration sensors near zero power when machinery is nominal. Anomaly wakes CPU in hardware reflex.

Details →
Space / Harsh

Radiation-Tolerant Edge

Deterministic 2-cycle wake with no firmware dependency. Hardware-level reliability in radiation-intensive environments.

Details →
IP Delivery

What You Receive

Full technical package delivered under NDA. RTL source, verification data, integration guide, and C-HAL driver — everything needed to evaluate and tape out.

Technical Package

NDA · delivered as secure archive

RTL — rpu_ultimate_final.sv

1,076 lines · SystemVerilog IEEE 1800-2017 · fully commented

C-HAL Driver

Pure C99 · no malloc · threshold / depth / mode configuration

ASIC PPA Reports

TSMC 65nm (Cadence Genus) + SkyWater SKY130 — timing, power, area

RISC-V Integration Data

Verilator logs · GTKWave waveforms · 3 benchmark scenarios

FPGA Measurement Data

Vivado Power Analyzer · Nexys A7-100T · LDR sensor comparison

Integration Guide

Step-by-step instantiation · parameter tuning · C-HAL examples

Licensing Options

Flexible terms · custom arrangements available

Evaluation License

Full RTL + docs for internal evaluation. Time-limited. NDA required.

Single-Product License

Full rights for one product line / tape-out. Includes C-HAL.

Portfolio License

Multiple product lines or unlimited tape-outs. Volume pricing.

Research / Academic

Post-IEEE-publication: Apache 2.0 GitHub. Pre-publication: contact us.

Integration Support

Parameter tuning, node optimization, co-design consulting available.

vs. Alternatives

What no existing technology delivers in one integrated block

Capability Software DVFS Conv. Clock Gating Wang 2024 HP Memristor RPU (This Work)
Decision originOS / FirmwareExternal monitorExternal FPGAPassive storageWithin the cell
Temporal change metricNoneNoneExternal ALUNoneO(1) combinational
Physical energy isolationNoClock onlyNoNoClock + Power ✓
Decision latencyms scaleExternal enableµs – msN/A1 clock cycle
Software / CPU requiredYesPartialYesN/AZero
Standard CMOSYesYesMemristiveMemristiveTSMC + SKY130 ✓
Autonomous adaptive thresholdNoNoFPGA-managedNoAsymmetric HW engine
Fail-safe pass-throughNoNoNoNoGuaranteed ✓
IP Status

Protected. Validated. Ready.

PCT international application with Turkish national priority. WIPO search benchmarked directly against HP and IBM patents — global novelty confirmed.

Turkish Priority · TR 2025/012696 · Sep 4, 2025
PCT · PCT/IB2026/053070 · Mar 27, 2026
WIPO: vs HP US 8,450,711 · IBM US 11,144,718 B2
IEEE TVLSI Under Review (2026)
Design & Reuse — design-reuse.com
TSMC 65nm + SkyWater SKY130
Apache 2.0 · post-publication

The cheapest computation is the one that never occurs.

Request the full technical validation package — PPA reports, RTL overview, RISC-V integration data, and silicon-proven metrics — under NDA.