A platform-agnostic synthesizable hardware IP that intercepts your data stream before the CPU. Works with any SoC, any node, any sector — without touching your existing system.
RPU operates as a fully independent block. You connect it in parallel with your existing data path — it observes your sensor bus and generates a single interrupt to your CPU when genuine change is detected.
Your SoC does not change. Your bus does not change. Your firmware does not change. If RPU is ever bypassed or removed, the system reverts to its previous polling behavior with zero added latency — guaranteed pass-through.
The entire integration is three parameter settings and two wire connections:
Not simulation-only. Two ASIC nodes, one live FPGA measurement, and a complete cycle-accurate RISC-V SoC integration.
0 ps WNS. 0 violating paths. 1.702 mW total. 2,960 gates. Cadence Genus. Critical path: 37 failing → 0 violations.
100 MHz. 0 ps WNS. 0.014 mW leakage — 0.35% of total. Identical RTL — no redesign required between nodes.
LDR sensor on Vivado Power Analyzer. Live data stream fed simultaneously to conventional circuit AND RPU. Direct hardware comparison, zero variables.
Cycle-accurate simulation. Wake latency: exactly 2 cycles in all scenarios.
| Scenario | Polling | RPU | Saving |
|---|---|---|---|
| Stable + Noise | 5,000,000 | 125 | 99.998% |
| Sudden Spike | 5,000,000 | 338 | 99.993% |
| Slow Drift | 5,000,000 | 1,487,143 | 70.3% |
The cheapest computation is the one that never occurs. RPU suppresses unnecessary computation at the source — before it propagates downstream.
Suppress stagnant returns at hardware layer. Guardian Sideband provides ungated watchdog on critical interrupt paths.
Details →LiDAR and camera stagnant frame suppression when vehicle is stationary. Zero latency penalty.
Details →Cardiac monitors, glucose sensors, environmental nodes. CPU stays in WFI until data actually changes.
Details →Suppress unchanged telemetry before it triggers CPU interrupts and context switches.
Details →Suppress stagnant tensors before GPU/TPU cycles are consumed. Static scene detection at front-end.
Details →Vibration sensors near zero power when machinery is nominal. Anomaly wakes CPU in hardware reflex.
Details →Deterministic 2-cycle wake with no firmware dependency. Hardware-level reliability in radiation-intensive environments.
Details →Full technical package delivered under NDA. RTL source, verification data, integration guide, and C-HAL driver — everything needed to evaluate and tape out.
1,076 lines · SystemVerilog IEEE 1800-2017 · fully commented
Pure C99 · no malloc · threshold / depth / mode configuration
TSMC 65nm (Cadence Genus) + SkyWater SKY130 — timing, power, area
Verilator logs · GTKWave waveforms · 3 benchmark scenarios
Vivado Power Analyzer · Nexys A7-100T · LDR sensor comparison
Step-by-step instantiation · parameter tuning · C-HAL examples
Full RTL + docs for internal evaluation. Time-limited. NDA required.
Full rights for one product line / tape-out. Includes C-HAL.
Multiple product lines or unlimited tape-outs. Volume pricing.
Post-IEEE-publication: Apache 2.0 GitHub. Pre-publication: contact us.
Parameter tuning, node optimization, co-design consulting available.
| Capability | Software DVFS | Conv. Clock Gating | Wang 2024 | HP Memristor | RPU (This Work) |
|---|---|---|---|---|---|
| Decision origin | OS / Firmware | External monitor | External FPGA | Passive storage | Within the cell |
| Temporal change metric | None | None | External ALU | None | O(1) combinational |
| Physical energy isolation | No | Clock only | No | No | Clock + Power ✓ |
| Decision latency | ms scale | External enable | µs – ms | N/A | 1 clock cycle |
| Software / CPU required | Yes | Partial | Yes | N/A | Zero |
| Standard CMOS | Yes | Yes | Memristive | Memristive | TSMC + SKY130 ✓ |
| Autonomous adaptive threshold | No | No | FPGA-managed | No | Asymmetric HW engine |
| Fail-safe pass-through | No | No | No | No | Guaranteed ✓ |
PCT international application with Turkish national priority. WIPO search benchmarked directly against HP and IBM patents — global novelty confirmed.
Request the full technical validation package — PPA reports, RTL overview, RISC-V integration data, and silicon-proven metrics — under NDA.